Test Papers

• Testable Design of Multiple-Stage OTA-C Filters

• Finding Ambiguity Groups in Low Testability Analog Circuits

• Test Point Selection for Analog Fault Diagnosis of Unpowered Circuit Boards

• Design-for-Testability Techniques for Detecting Delay Faults in CMOS/BiCMOS Logic Families

• Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays

• Testing and Testable Designs for One-Time Programmable FPGAs

• BIST Hardware Synthesis for RTL Data Paths Based on Test Compatibility Classes

• Low-Power Weighted Random Pattern Testing

• A New Approach to Built-In Self-Testable Datapath Synthesis Based on Integer Linear Programming

• Improving Path Delay Testability of Sequential Circuits

• Analysis and Generation of Control and Observation Structures for Analog Circuits

• Software-Based Self-Testing Methodology for Processor Cores

• Testing of Core-Based Systems-on-a-Chip

• Bit-Fixing in Pseudorandom Sequences for Scan BIST

• System-on-Chip Testability Using LSSD Scan Structures

• Boundary-Scan Bursts into the Production Facility

• Testing of Scan Circuits Containing Nonisolated Random-Logic Legacy Cores

• Open Systems architecture solutions For Military Avionics Testing

• System-Level Test Synthesis for Mixed-Signal Designs

• Very Low Cost Testers: Opportunities and Challenges

• Resynthesis of Combinational Logic Circuits for Improved Path Delay Fault Testability Using Comparison Units

• Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures

• Prioritizing Test Cases For Regression Testing

• On Comparisons of Random, Partition, and Proportional Partition Testing

• Strategies for Low-Cost Test

• TAO: Regular Expression-Based Register-Transfer Level Testability Analysis and Optimization

• EROS: A Principle-Driven Operating System from the Ground Up

• Test Generation and testability Alternatives, Exploration of Critical Algorithms for Embedded Applications

• Modeling the Economics of Testing: A DFT Perspective

• Analysis of a BICS-only concurrent error Detection Method

• A 4-GHz Effective Sample Rate Integrated Test Core for Analog and Mixed-Signal Circuits

• DFT and BIST of a Multichip Module for High-Energy Physics Experiments

• Statistical Threshold Formulation for Dynamic Idd Test

• Test Compaction for At-Speed Testing of Scan Circuits Based on Nonscan Test Sequences and Removal of Transfer Sequences

• Test Bus Sizing for system-on-a-Chip

• Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits

• Incremental Integration Testing of Concurrent Programs

• A Comprehensive Approach to the Partial Scan Problem Using Implicit State Enumeration

• High-Level Test Compaction Techniques

• 0.13-_m 32-Mb/64-Mb Embedded DRAM CoreWith High Efficient Redundancy and Enhanced Testability

• Nanometer Mixed-Signal System-on-a-Chip Design

• Handling the Pin Overhead Problem of DFTs for High-Quality and At-Speed Tests

• Software Testing

• High Defect Coverage with Low-Power Test Sequences in a BIST Environment

• Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers

• Dynamic Scan: Driving Down the Cost of Test

• Efficient FFT Network Testing and Diagnosis Schemes

• Test Synthesis of Systems-on-a-Chip

• The Digital Front-End Electronics for the Space-Borne INTEGRAL-SPI Experiment: ASIC Design, Design for Test Strategies and Self-Test Facilities

• Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures

• Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell

• Formulating SoC Test Scheduling as a Network Transportation Problem

• Optimization of Short-Flow MOS Charging Monitor for Ion Implantation

• An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs

• Circular BIST With State Skipping

• Layout Driven Synthesis of Multiple Scan Chains

• Testing ASICs with Multiple Identical Cores

• A Unified Approach to Reduce SOC Test Data Volume, Scan Power and Testing Time

• Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction

• Partial BIST Insertion to Eliminate Data Correlation

• Test-Suite Reduction and Prioritization for Modified Condition/Decision Coverage

• Relative Timing

• A Singular-Value Decomposition Approach for Ambiguity Group Determination in Analog Circuits

• A Synthesis-for-Transparency Approach for Hierarchical and System-on-a-Chip Test

• A Test Evaluation Technique for VLSI Circuits Using Register-Transfer Level Fault Modeling

• Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution

• A Test Evaluation Technique for VLSI Circuits Using Register-Transfer Level Fault Modeling

• A Novel Approach to Random Pattern Testing of Sequential Circuits

• Design for Testability of Embedded Integrated Operational Amplifiers

• Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings

• Test Data Compression and Test Time Reduction Using an Embedded Microprocessor

• Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test

• Single-Clock, Single-Latch, Scan Design

• ATPG for Heat Dissipation Minimization During Test Application

• Testing Configurable LUT-Based FPGA’s

• Control and Observation Structures for Analog Circuits

• A Unified Design Methodology for Offline and Online Testing

• A Controller Redesign Technique to Enhance Testability of Controller-Data Path Circuits

• Empirical Studies of a Safe Regression Test Selection Technique

• A High-Q Bandpass Fully Differential SC Filter with Enhanced Testability

• Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test Points

• Hardware-Optimal Test Register Insertion

• Optimal and Near-Optimal Algorithms for Multiple Fault Diagnosis with Unreliable Tests

• Testability Features of the AMD-K6 Microprocessor

• Testability Analysis and Behavioral Testing of the Hopfield Neural Paradigm

• Efficient BIST TPG Design and Test Set Compaction via Input Reduction

• A Design-for-Testability Technique for Register-Transfer Level Circuits Using Control/Data Flow Extraction

• Cost-Free Scan: A Low-Overhead Scan Path Design

• On the Application of Symbolic Techniques to the Multiple Fault Location in Low Testability Analog Circuits

• A Tutorial Introduction to Research on Analog and Mixed-Signal Circuit Testing

• Economics Modeling of Multichip Modules Testing Strategies

• Integrated Circuit Signal Measurements Using an Undersampling Approach

• Integration of Hierarchical Test Generation with Behavioral Synthesis of Controller and Data Path Circuits

• A New Symbolic Method for Analog Circuit Testability Evaluation

• Test Sequencing Problems Arising in Test Planning and Design for Testability

• Hierarchical Test Generation and Design for Testability Methods for ASPP’s and ASIP’s

• Test in the Emerging Intellectual Property Business

• Fault Models and Tests for a 2-Bit-per-Cell MLDRAM

• Comments on “Linear Circuit Fault Diagnosis Using Neuromorphic Analyzers”

• Field Motor Testing

• Resynthesis and Retiming for Optimum Partial Scan

• Redundancy and Testability in Digital Filter Datapaths

• Primitive Delay Faults: Identification, Testing, and Design for Testability

• Combining Multiple DFT Schemes with Test Generation

• A Cost-Effective Design For Testability: Clock Line Control and Test Generation Using Selective Clocking

• Universal Delay Test Sets for Logic Networks

• Built-in Self Test

• Making Complex- Mixed Signal Telecommunication Integrates Circuits Testable

• Synthesis of Modular Mechatronic Products: A Testability Perspective

• Automatic Analog Test Signal Generation Using Multifrequency Analysis

• Determination of an Optimum Set of Testable Components in the Fault Diagnosis of Analog Linear Circuits

• Implementation of a Self-Resetting CMOS 64-Bit Parallel Adder with Enhanced Testability

• Oscillation-Test Methodology for Low-Cost Testing of Active Analog Filters

• Diagnosis of Scan Cells in BIST Environment

• Testability Analysis and Test-Point Insertion in RTL VHDL Specifications for Scan-Based BIST

• Design for Test and Time to Market: A Personal Perspective

• Partial Scan with Preselected Scan Signals

• Nanometer technology: Challenges for test and test equipment

• Concurrent directions for automatic Test Pattern Generation

• Robust Scan-Based logic Test in VDSM Technologies

• A Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems-on-a-Chip

• Using Built-in Test to reduce TPS Run Times and improve TPS Reliability

• A Synthesis for Testability Scheme for FiniteState Machines Using Clock Control

• Broadcasting Test Patterns to Multiple Circuits

• Partition Testing vs. Random Testing:The Influence of Uncertainty

• Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal

• An Approach for Detecting Multiple Faulty FPGA Logic Blocks

• A BIST Scheme for RTL Circuits Based on Symbolic Testability Analysis

• IC Test Using the Energy Consumption Ratio

• TAIR: Testability Analysis by Implication Reasoning

• On the Design of Fast, Easily Testable ALU’s

• Advanced Controlling Scheme for a DRAM Voltage Generator System

• A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits

• Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability

• A Hierarchical Test Generation Approach For large Controllers

• On The Statistical testing of Solid Insulation Systems

• Efficient Object-Oriented Integration and Regression Testing

• A Fast and Low-Cost Testing Technique for Core-Based System-Chips

• TAO-BIST: A Framework for Testability Analysis and Optimization for Built-In Self-Test of RTL Circuits

• Enabling Testability of Fault-Tolerant Circuits by Means of -Checkable Voters

• Star Test: The Theory and Its Applications

• The Mutating Metric for Benchmarking Test

• RT-level ITC’99 Benchmarks and First ATPG Results

• First Results of ITC’99 Benchmark Circuits

• High-Speed Easily Testable Galois-Field Inverter

• Easily Testable and Fault-Tolerant FFT Butterfly Networks